The present invention relates to a semiconductor memory device, and more particularly to a row address controller.
As generally known in the art, a dynamic random access memory (DRAM), which is a semiconductor memory device, is a volatile memory device including a plurality of cells, each cell containing one transistor and one capacitor.
Recently, as DRAMs have been highly integrated, studies have been conducted to develop a DRAM using less current and having a higher efficiency by simplifying the control unit controlling the operation of the DRAM.
Meanwhile, a DRAM, which is a conventional semiconductor memory device, receives external commands “/RAS,” “/CAS” and “/WE” input from an exterior source, and creates or generates internal command pulses. The internal command pulses enable the internal operation of the DRAM to be controlled at a proper time.
The DRAM, which is a conventional memory device, delays and uses a created internal command pulse in order to generate a different control signal required for the operation of the DRAM.
For example, the DRAM delays an active pulse created in the DRAM according to an external active command, and a precharge pulse created in the DRAM according to an external precharge command, and generates a control signal for a row address processing control. Such an operation of the DRAM will now be described with respect to the bank control unit of a conventional row address controller.
FIG. 1 is a block diagram illustrating the construction of the bank control unit 10 in a conventional row address controller. Referring to FIG. 1, the bank control unit 10 of the conventional row address controller receives an active pulse “ACT13,” and generates an ACT14 pulse, an ACT16 pulse and an ACT22 pulse, through a plurality of delay units. In addition, the bank control unit receives a precharge pulse “PCG12,” and generates a PCG15 pulse, a PCG19 pulse and a PCG21 pulse, through a plurality of delay units.
The plurality of delay units requires many transistors, thereby degrading the efficiency of a memory cell. Also, the pulses generated through such a delay cause toggle of an address signal, thereby causing unnecessary current consumption in a row address decoder.
The problem of a conventional row address controller will now be described in more detail.
FIG. 2 is a block diagram illustrating the construction of a conventional row address controller 20, and FIG. 3 is a timing view illustrating the operation of the row address controller shown 20 in FIG. 2. Referring to FIGS. 2 and 3, the bank control unit receives an active pulse “ACT13” and a precharge pulse “PCG13,” and generates and outputs an ACT16 pulse, a PCG19 pulse, a word line clear signal “WLCB” and a block selection enable signal “BSENB.” An address enable signal generating unit receives the ACT16 pulse and PCG19 pulse, and generates and outputs address enable signals “BXADDENB” and “BXADDEN_COM.”
The bank control unit and address enable signal generating unit use a plurality of delay units in order to generate these signals, that is, the ACT16 pulse, the PCG19 pulse, the word line clear signal “WLCB,” the block selection enable signal “BSENB” and the address enable signals “BXADDENB” and “BXADDEN_COM.” Therefore, the area occupied by the delay units increases within an X cross region in which the bank control unit and address enable signal generating unit are located.
The signals generated by the bank control unit and address enable signal generating unit are input to different blocks, such as a block selection unit, first and second latch units, and a word line enable control unit, which are located in an X hole region, for a row address processing control, and are used to generate control signals for a sub-word line driver, a main word line driver and a redundancy word line driver.
A row address decoder receives the address enable signal “BXADDEN_COM,” and outputs signal “BAX34,56,78” and signal “BAX9AB” to first and second latch units, respectively. The signals “BAX34, 56, 78” and “BAX9AM” are obtained by decoding row address GAX<0:11>, The first latch unit receives the address enable signal “BXADDENB,” and latches and outputs the signal “BAX34,56,78” to the main word line driver. The second latch unit latches and outputs the signal “BAX012” to the sub-word line driver.
Address “LAX34,56,78” and address “LAX012,” which are latched by the first and second latch units, are logically operated with a block selection signal “BSB” of the block selection unit, a word off signal “LXDPB” of a delay unit and output signals “MWLEN” and “RMWLEN” of the word line enable control unit, in the sub-word line driver, main word line driver and redundancy word line driver, thereby enabling a sub-word line, a main word line and a redundancy word line.
In the conventional row address controller, various related signals have insufficiently coherent relation, which may cause lack in the margin according to a skew of each signal, thereby causing failure. For example, the main word line driver performs a logic operation with respect to the word off signal “LXDPB” and main word line enable signal “MWLEN” during a time period in which signal “LAX34,56,78” is latched by the first latch unit and is output as a valid signal, thereby generating a main word line driving signal “MWLB.”
Herein, while the block selection signal “BSB” is related to both the generation of the word off signal “LXDPB” and the generation of the main word line enable signal “MWLEN,” the block selection enable signal “BSENB” is related to only the generation of the main word line enable signal “MWLEN.” Therefore, the main word line driving signal “MWLB” must secure a margin for the word off signal “LXDPB” and main word line enable signal “MWLEN,” and must also take into consideration a margin for other signals relating to the word off signal “LXDPB” and main word line enable signal “MWLEN.”
Meanwhile, the “BAX34,56,78” is generated through a logic operation with respect to the row address GAX<0:11> and the address enable signal “BXADDEN_COM” in the address decoder, and has a valid address value only in a period in which the address enable signal “BXADDENB” is enabled. Therefore, the “BAX34,56,78” generates toggle of an address signal in the same phase shape as that of the address enable signal “BXADDENB.” The address toggle of the “BAX34,56,78” serves as a cause of current consumption in the row address decoder. “BAX34<0>” and “BAX34<1>” in the timing view illustrate a case in which the toggle of an address signal is caused.